IEEE P1076 Working Group: VHDL Analysis and Standardization Group (VASG)¶
IEEE P1076 Working Group VHDL Analysis and Standardization Group (VASG)
The VHDL Analysis and Standardization Group (VASG) is responsible for maintaining and extending the VHDL standard (IEEE 1076), which is delivered as a Language Reference Manual (LRM) along with Packages (standard and IEEE libraries).
The Working Group is starting to identify issues to work on for the next 202X revision of the standard, in order to prepare a Project Authorization Request (PAR).
If you are a VHDL user, digital designer, or verification engineer, then this is your working group.
P1076 is an individual based standard. The only requirement for membership is to show up through any of the communication channels, and participate. There are no fees required.
Work is done in on-line Meetings, Email Reflector/List, Chat rooms (Gitter), GitLab Repositories (newer stuff), TWIKI site (older stuff), etc. All of this permits you to contribute what you can when you can.
We seek volunteers experienced in one or more:
(V)HDL design and/or verification
Language design (VHDL, Ada, C, Python…)
Programming Language Interfaces (VHPI, VPI, DPI, FFI…)
Digital design experience (DSP, Floating-Point, Machine-Learning…)
GitLab API, Sphinx, Continuous Integration…
We need all skills, including users who can say ‘I will use that feature if you make it!’. While we always need experienced VHDL users to participate, currently we also need LaTeX users to help out.
If you are interested in contributing, see the Help Wanted page for current needs.
Moreover, we would like any VHDL user to submit enhancement requests, proposals, or bug reports for 202X. Join us and help create the next VHDL standards!
Releases of VHDL libraries are published at opensource.ieee.org/vasg/Packages (since December 2019)
In order to reach a wider audience, the VASG uses an organization in GitLab: gitlab.com/IEEE-P1076